1、抢答鉴别模块FENG的VHDL源程序
--feng.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY FENG IS
PORT(CP,CLR:IN STD_LOGIC
Q :OUT STD_LOGIC)
END FENG
ARCHITECTURE FENG_ARC OF FENG IS
BEGIN
PROCESS(CP,CLR)
BEGIN
IF CLR='0'THEN
Q<='0'
ELSIF CP'EVENT AND CP='0'没闷THEN
Q<='1'
END IF
END PROCESS
END FENG_ARC
2、片选信号产生模块悔睁SEL的VHDL源程序
--sel.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY SEL IS
PORT(CLK:IN STD_LOGIC
a:OUT INTEGER RANGE 0 TO 7)
END SEL
ARCHITECTURE SEL_ARC OF SEL IS 片选信号产生模块SEL
BEGIN
PROCESS(CLK)
VARIABLE AA:INTEGER RANGE 0 TO 7
BEGIN
IF CLK'EVENT AND CLK='1'THEN
AA:=AA+1
END IF
A<=AA
END PROCESS
END SEL_ARC
3、锁存器模块LOCKB的VHDL源程序
-lockb.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY LOCKB IS
PORT(D1,D2,D3,D4:IN STD_LOGIC
CLK,CLR:IN STD_LOGIC
Q1,Q2,Q3,Q4,ALM:OUT STD_LOGIC)
END LOCKB
ARCHITECTURE LOCK_ARC OF LOCKB IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLR='0'THEN
Q1<='0'
Q2<='0'
Q3<='0'
Q4<='0'碧察岁
ALM<='0' 模块LOCKB
ELSIF CLK'EVENT AND CLK='1'THEN
Q1<=D1
Q2<=D2
Q3<=D3
Q4<=D4
ALM<='1'
END IF
END PROCESS
END LOCK_ARC
4、转换模块CH41A的VHDL源程序
--ch41a..vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY CH41A IS
PORT(D1,D2,D3,D4:IN STD_LOGIC
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0))
END CH41A
ARCHITECTURE CH41_ARC OF CH41A IS 转换模块CH41A
BEGIN
PROCESS(D1,D2,D3,D4)
VARIABLE TMP:STD_LOGIC_VECTOR(3 DOWNTO 0)
BEGIN
TMP:=D1&D2&D3&D4
CASE TMP IS
WHEN "0111"=>Q<="0001"
WHEN "1011"=>Q<="0010"
WHEN "1101"=>Q<="0011"
WHEN "1110"=>Q<="0100"
WHEN OTHERS=>Q<="1111"
END CASE
END PROCESS
END CH41_ARC
5、3选1模块CH31A的VHDL源程序
--ch31a.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY CH31A IS
PORT(SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0)
D1,D2,D3:IN STD_LOGIC_VECTOR(3 DOWNTO 0)
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0))
END CH31A
ARCHITECTURE CH31_ARC OF CH31A IS
BEGIN
PROCESS(SEL,D1,D2,D3)
BEGIN
CASE SEL IS
WHEN "000"=>Q<=D1
WHEN "001"=>Q<=D2
WHEN "111"=>Q<=D3
WHEN OTHERS=>Q<="1111"
END CASE
END PROCESS
END CH31_ARC
6、倒计时模块COUNT的VHDL源程序
倒计时模块COUNT如图16-7所示，该模块实现答题时间的倒计时，在计满100s后送出声音提示。
--count.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY COUNT IS
PORT(CLK,EN:IN STD_LOGIC倒计时 模块COUNT
H,L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
SOUND:OUT STD_LOGIC)
END COUNT
ARCHITECTURE COUNT_ARC OF COUNT IS
BEGIN
PROCESS(CLK,EN)
VARIABLE HH,LL:STD_LOGIC_VECTOR(3 DOWNTO 0)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF EN='1'THEN
IF LL=0 AND HH=0 THEN
SOUND<='1'
ELSIF LL=0 THEN
LL:="1001"
HH:=HH-1
ELSE
LL:=LL-1
END IF
ELSE
SOUND<='0'
HH:="1001"
LL:="1001"
END IF
END IF
H<=HH
L<=LL
END PROCESS
END COUNT_ARC
7、显示译码模块DISP的VHDL源程序
--disp.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY DISP IS 显示译码模块DISP
PORT(D:IN STD_LOGIC_VECTOR(3 DOWNTO 0)
Q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0))
END DISP
ARCHITECTURE DISP_ARC OF DISP IS
BEGIN
PROCESS(D)
BEGIN
CASE D IS
WHEN"0000"=>Q<="0111111"
WHEN"0001"=>Q<="0000110"
WHEN"0010"=>Q<="1011011"
WHEN"0011"=>Q<="1001111"
WHEN"0100"=>Q<="1100110"
WHEN"0101"=>Q<="1101101"
WHEN"0110"=>Q<="1111101"
WHEN"0111"=>Q<="0100111"
WHEN"1000"=>Q<="1111111"
WHEN"1001"=>Q<="1101111"
WHEN OTHERS=>Q<="0000000"
END CASE
END PROCESS
END DISP_ARC
7位抢答器设计：LIBRARY IEEE；
USE IEEE.Std_logic_1164.ALL；
ENTITY Responder IS -- 实体声明
PORT（Start：IN Std_logic； -- 端口声明
Key：IN Std_logic_Vector(7 DOWNTO 1)；
Led：OUT Std_logic_Vector(7 DOWNTO 1))；
END Responder；
ARCHITECTURE behave OF Responder IS -- 结构体声野猛明
SIGNAL mask_off：Std_logic；-- 信号声明
BEGIN
P1：PROCESS（Start，Key）-- 进程语句
BEGIN
IF Start = '0' THEN -- 行为描述
mask_off <= ‘0’； -- 起始信号Start复位mask_off信号
ELSIF (Key = "1111110" OR Key = "1111101" OR Key = "1111011" OR
Key = "1110111" OR Key = "1101111" OR Key = "1011111" OR
Key = "0111111") THEN
mask_off <= ‘1’； -- 某一按键按下则令mask_off信号出现上升沿
END IF；
END PROCESS；
P2：PROCESS（Start，mask_off） -- 进程语句
BEGIN
IF Start = '0' THEN-- 行为描述
Led <=（OTHERS =>‘0’）； -- 7D触发器异步复位
ELSIF Rising_Edge (mask_off) THEN-- 出现mask_off信号上升沿
Led <颂物桥= NOT Key； -- 7D触蚂竖发器锁存Key(7)~Key(1)
END IF；
END PROCESS；
END behave；
如果上面的描述中包含有全角符号的话，你将其改成半角符号即可。
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