FPGA VHDL语言 50Mhz 改2hz 8hz 分频

library ieee;
use ieeestd_logic_1164all;
use ieeestd_logic_unsignedall;
entity div is
generic(n:integer :=6250000);
port (clk:in std_logic;
q:out std_logic);
end div;
architecture behav of div is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk)
begin
if (clk'event and clk='1' and clk'last_value ='0') then
count<=count-1;
if count>=n/2 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behav;
entity ferq_div is
port (clk:in std_logic;
q_2Hz, q_8Hz:out std_logic);
end freq_div;
architecture top of freq_div is
SIGNAL q: std_logic;
begin
U_8: div port map( clk => clk, q => q);
U_2: div generic map( n => 4) port map(clk => q, q => q_2Hz);
q_8Hz <= q;
end top;

有3种办法：

直接利用开发工具（Quartus II或者ISE）中的IP Core将50MHz的时钟信号分频至15MHz；

先利用开发工具（Quartus II或者ISE）中的IP Core将50MHz的时钟信号3倍频至150MHz，然后再将其10分频，就得到15MHz的时钟分支信号了；

采用锁相环技术设计非整数分频电路，参阅《FPGA/CPLD应用设计200例》（上册）p354~357，北京航空航天大学出版社2009年出版。

library ieee;
use ieeestd_logic_1164all;
entity div is
generic(n:integer :=50);
port (clk,reset_n:in std_logic;
q:out std_logic);
end div;
architecture behave of div is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk,reset_n)
begin
if reset_n='0' then
count <= n-1;
elsif rising_edge(clk) then
count<=count-1;
if count>=n/2 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behave;

LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
USE IEEESTD_LOGIC_ARITHALL;
USE IEEESTD_LOGIC_UNSIGNEDALL;
ENTITY fq_divider IS
generic(n:integer:=60000);
PORT(
CLK,reset: IN STD_LOGIC;
CLK_OUT:buffer STD_LOGIC
);
END;
ARCHITECTURE A OF fq_divider IS
SIGNAL CNT1,CNT2:integer:=0;
SIGNAL OUTTEMP:STD_LOGIC;
SIGNAL LOUT:STD_LOGIC;
SIGNAL OUT3:STD_LOGIC:='0';
BEGIN
P1:PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT1=n-1 THEN
CNT1<=0;
ELSE
CNT1<=CNT1+1;
END IF;
END IF;
END PROCESS P1;
P2:PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='0' THEN
IF CNT2=n-1 THEN
CNT2<=0;
ELSE
CNT2<=CNT2+1;
END IF;
END IF;
END PROCESS P2;
P3:PROCESS(CNT1,CNT2 )
BEGIN
if ((n mod 2)=1) then
IF CNT1=1 THEN
IF CNT2=0 THEN
OUTTEMP<='1';
ELSE
OUTTEMP<='0';
END IF;
ELSIF CNT1=(n+1)/2 THEN
IF CNT2=(n+1)/2 THEN
OUTTEMP<='1';
ELSE OUTTEMP<='0';
END IF;
ELSE
OUTTEMP<='0';
END IF;
else
if cnt1=1 then
outtemp<='1';
elsif (cnt1=(n/2+1)) then
outtemp<='1';
else
outtemp<='0';
end if;
end if;
END PROCESS P3;
P4:PROCESS(OUTTEMP,clk,reset)
BEGIN
if reset='0' then
clk_out<=clk;
elsif ((n/=2) and (n/=1)) then
IF OUTTEMP'EVENT AND OUTTEMP='1' THEN
CLK_OUT<=NOT CLK_OUT;
END IF;
elsif (n=2) then
if(clk'event and clk='1')then
clk_out<=not clk_out;
end if;
else
clk_out<=clk;
end if;
END PROCESS P4;
END A;

这是我这次毕业设计的部分分频模块，绝对可用，很简单的。
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
USE IEEESTD_LOGIC_SIGNEDALL;
ENTITY fenpin IS
PORT(cp_50m:IN STD_LOGIC; --50MHz 输入50MHz
cp0:OUT STD_LOGIC; --1MHz 输出1MHz
cp1:OUT STD_LOGIC); -4s
END fenpin;
ARCHITECTURE behavior OF fenpin IS
SIGNAL tout0:INTEGER RANGE 0 TO 49; --50分频
SIGNAL tout1:INTEGER RANGE 0 TO 999999; --1Hz
SIGNAL tout2:INTEGER RANGE 0 TO 3; --3s高电平，1s低电平
SIGNAL cp_0:STD_LOGIC;
SIGNAL cp_1:STD_LOGIC;
SIGNAL cp_2:STD_LOGIC;
BEGIN
PROCESS(cp_50m) --1MHz
BEGIN
IF(cp_50m'event AND cp_50m='1')THEN
IF tout0=49 THEN
tout0<=0;
ELSE tout0<=tout0+1;
END IF;
IF tout0=24 THEN
cp_0<='1';
ELSIF tout0=49 then cp_0<='0';
END IF;
END IF;
END PROCESS;
PROCESS(cp_0) --1Hz
BEGIN
IF(cp_0'event AND cp_0='1')THEN
IF tout1=999999 THEN
tout1<=0;
ELSE tout1<=tout1+1;
END IF;
IF tout1=999999 THEN
cp_1<='1';
ELSIF tout1=499999 then cp_1<='0';
END IF;
END IF;
END PROCESS;
PROCESS(cp_1) --4s
BEGIN
IF(cp_1'event AND cp_1='1')THEN
IF tout2=3 THEN
tout2<=0;
ELSE tout2<=tout2+1;
END IF;
IF tout2=3 THEN
cp_2<='1';
ELSIF tout2=2 then cp_2<='0';
END IF;
END IF;
END PROCESS;
cp0<=cp_0;cp1<=cp_2;
END behavior;

library ieee;
use ieeestd_logic_1164all;
entity oneMHZ is
port( clkin:in std_logic; --时钟信号输入
clkout:out std_logic); --时钟信号输出
end oneMHZ;
architecture aroneMHZ of oneMHZ is
signal data:integer range 0 to 10;
signal Q:std_logic;
begin
process(clkin)
begin
if rising_edge(clkin) then
if(data=0) then －－此句为你想要的分频比，data=0,1,2,3,49的分频比为1,2，3，，,10
data<=0;
Q<=not Q;
else
data<=data+1;
end if;
end if;
clkout<=Q;
end process;
end oneMHZ;

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