VHDL怎么用程序包package

你可以把package文件放在当前的工程中，在顶层文件调用包时声明一下：
use workpackage_nameall；work就是当前库，或者你在你的开发环境中将你的包集保存到ieee库文件中，然后从ieee库中调用，use ieeepackage_nameall 灵活性很大

各模块VHDL源代码
1、抢答鉴别模块FENG的VHDL源程序
--fengvhd
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
ENTITY FENG IS
PORT(CP,CLR:IN STD_LOGIC;
Q :OUT STD_LOGIC);
END FENG;
ARCHITECTURE FENG_ARC OF FENG IS
BEGIN
PROCESS(CP,CLR)
BEGIN
IF CLR='0'THEN
Q<='0';
ELSIF CP'EVENT AND CP='0'THEN
Q<='1';
END IF;
END PROCESS;
END FENG_ARC;
2、片选信号产生模块SEL的VHDL源程序
--selvhd
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
ENTITY SEL IS
PORT(CLK:IN STD_LOGIC;
a:OUT INTEGER RANGE 0 TO 7);
END SEL;
ARCHITECTURE SEL_ARC OF SEL IS 片选信号产生模块SEL
BEGIN
PROCESS(CLK)
VARIABLE AA:INTEGER RANGE 0 TO 7;
BEGIN
IF CLK'EVENT AND CLK='1'THEN
AA:=AA+1;
END IF;
A<=AA;
END PROCESS;
END SEL_ARC;
3、锁存器模块LOCKB的VHDL源程序
-lockbvhd
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
ENTITY LOCKB IS
PORT(D1,D2,D3,D4:IN STD_LOGIC;
CLK,CLR:IN STD_LOGIC;
Q1,Q2,Q3,Q4,ALM:OUT STD_LOGIC);
END LOCKB;
ARCHITECTURE LOCK_ARC OF LOCKB IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLR='0'THEN
Q1<='0';
Q2<='0';
Q3<='0';
Q4<='0';
ALM<='0'; 模块LOCKB
ELSIF CLK'EVENT AND CLK='1'THEN
Q1<=D1;
Q2<=D2;
Q3<=D3;
Q4<=D4;
ALM<='1';
END IF;
END PROCESS;
END LOCK_ARC;
4、转换模块CH41A的VHDL源程序
--ch41avhd
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
ENTITY CH41A IS
PORT(D1,D2,D3,D4:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CH41A;
ARCHITECTURE CH41_ARC OF CH41A IS 转换模块CH41A
BEGIN
PROCESS(D1,D2,D3,D4)
VARIABLE TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
TMP:=D1&D2&D3&D4;
CASE TMP IS
WHEN "0111"=>Q<="0001";
WHEN "1011"=>Q<="0010";
WHEN "1101"=>Q<="0011";
WHEN "1110"=>Q<="0100";
WHEN OTHERS=>Q<="1111";
END CASE;
END PROCESS;
END CH41_ARC;
5、3选1模块CH31A的VHDL源程序
--ch31avhd
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
ENTITY CH31A IS
PORT(SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
D1,D2,D3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CH31A;
ARCHITECTURE CH31_ARC OF CH31A IS
BEGIN
PROCESS(SEL,D1,D2,D3)
BEGIN
CASE SEL IS
WHEN "000"=>Q<=D1;
WHEN "001"=>Q<=D2;
WHEN "111"=>Q<=D3;
WHEN OTHERS=>Q<="1111";
END CASE;
END PROCESS;
END CH31_ARC;
6、倒计时模块COUNT的VHDL源程序
倒计时模块COUNT如图16-7所示，该模块实现答题时间的倒计时，在计满100s后送出声音提示。
--countvhd
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
USE IEEESTD_LOGIC_UNSIGNEDALL;
ENTITY COUNT IS
PORT(CLK,EN:IN STD_LOGIC; 倒计时 模块COUNT
H,L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SOUND:OUT STD_LOGIC);
END COUNT;
ARCHITECTURE COUNT_ARC OF COUNT IS
BEGIN
PROCESS(CLK,EN)
VARIABLE HH,LL:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF EN='1'THEN
IF LL=0 AND HH=0 THEN
SOUND<='1';
ELSIF LL=0 THEN
LL:="1001";
HH:=HH-1;
ELSE
LL:=LL-1;
END IF;
ELSE
SOUND<='0';
HH:="1001";
LL:="1001";
END IF;
END IF;
H<=HH;
L<=LL;
END PROCESS;
END COUNT_ARC;
7、显示译码模块DISP的VHDL源程序
--dispvhd
LIBRARY IEEE;
USE IEEESTD_LOGIC_1164ALL;
ENTITY DISP IS 显示译码模块DISP
PORT(D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END DISP;
ARCHITECTURE DISP_ARC OF DISP IS
BEGIN
PROCESS(D)
BEGIN
CASE D IS
WHEN"0000"=>Q<="0111111";
WHEN"0001"=>Q<="0000110";
WHEN"0010"=>Q<="1011011";
WHEN"0011"=>Q<="1001111";
WHEN"0100"=>Q<="1100110";
WHEN"0101"=>Q<="1101101";
WHEN"0110"=>Q<="1111101";
WHEN"0111"=>Q<="0100111";
WHEN"1000"=>Q<="1111111";
WHEN"1001"=>Q<="1101111";
WHEN OTHERS=>Q<="0000000";
END CASE;
END PROCESS;
END DISP_ARC;

题主想问的是安卓手机使用vhd文件的虚拟机怎么使用？
1、进入Unity模式，你在虚拟机里打开的窗口全都变成了在正常系统的任务栏里即可。
2、Java虚拟机是Java语言底层实现的基础，对Java语言感兴趣的人都应对Java虚拟机有个大概的了解。这有助于理解Java语言的一些性质，也有助于使用Java语言。对于要在特定平台上实现Java虚拟机的软件人员。
3、windowsXP虚拟机vmware下安装Linux我们在实际的WindowsXP中(宿主计算机)再虚拟出一台电脑(虚拟机)，并在上面安装Linux系统。
4、这样，你就可以放心大胆地进行各种Linux练习而无须担心 *** 作不当导致宿主机系统崩溃了。并且你可以举一反三，将一台电脑变成三台、四台，再分别安装上其他的系统。(运行虚拟机软件的 *** 作系统叫HostOS，在虚拟机里运行的 *** 作系统叫GuestOS)。

帮你改了一下，只做了编译，没做仿真，你的源程序少了几条关键的语句，帮你加了。不过好像比上面的同志慢了点儿，哈哈。反正也做了。第二个程序没有问题。
library ieee;
use IEEEstd_logic_1164all;
use IEEEstd_logic_unsignedall;
use IEEEstd_logic_arithall;
entity counter_t is
generic(width : integer := 8);
port( data : in std_logic_vector (width-1 downto 0);
load, en, clk, rst : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end counter_t;
architecture behave of counter_t is
signal count : std_logic_vector (width-1 downto 0);
component m is
port( data : in std_logic_vector (width-1 downto 0); --这里，实体m中的DATA没有声明
rst,clk,load,en:in std_logic ;
count : out std_logic_vector (width-1 downto 0));
end component m;
begin
u1: m port map(data,rst,clk,load,en,count);
end behave;
library ieee;
use ieeestd_logic_1164all;
use ieeestd_logic_unsignedall;
entity m is
generic(width : integer := 8);
port( data : in std_logic_vector( width-1 downto 0); --对结构体中的DATA进行声明
rst,clk,load,en:in std_logic ;
count : out std_logic_vector (width-1 downto 0));
end m;
architecture behave of m is
signal c : std_logic_vector (width-1 downto 0);
begin
process( clk,rst ) --要有进程开始
begin
if rst = '1' then
c <=(others=>'0'); --清零
elsif rising_edge(clk) then --上升沿检测
if load = '1' then
c <= data;
elsif en = '1' then
c <= c + '1';
end if;
end if;
end process; --要有进程结束
count <= c;
end behave;

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