用VHDL语言设计一个4位二进制数据比较器，应该怎么设计？

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY COMPARE4 IS                        ——四位比较器

PORT(IA_MORE_THAN_B:IN STD_LOGIC    ——高位比较的标志位的输入

IB_MORE_THAN_A:IN STD_LOGIC

IA_EQUAL_B:IN STD_LOGIC

A:IN STD_LOGIC_VECTOR(3 DOWNTO 0)——两个输入

B:IN STD_LOGIC_VECTOR(3 DOWNTO 0)

OA_MORE_THAN_B:OUT STD_LOGIC

OB_MORE_THAN_A:OUT STD_LOGIC

OA_EQUAL_B:OUT STD_LOGIC)

END COMPARE4

ARCHITECTURE BEHAV OF COMPARE4 IS

BEGIN

PROCESS(IB_MORE_THAN_A, IA_EQUAL_B,IA_EQUAL_B)

BEGIN

IF(IA_EQUAL_B='1')THEN

——从最高位比较，如果高位大则停止比较输出结果，否则进行下一位比较

IF(A(3)>B(3))THEN              

OA_MORE_THAN_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0'

ELSIF(A(3)<B(3))THEN

OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA_EQUAL_B<='0'

ELSIF(A(2)>B(2))THEN

OA_MORE_THAN_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0'

ELSIF(A(2)<B(2))THEN

OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA_EQUAL_B<='0'

ELSIF(A(1)>B(1))THEN

OA_MORE_THAN_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0'

ELSIF(A(1)<B(1))THEN

OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA_EQUAL_B<='0'

ELSIF(A(0)>B(0))THEN

OA_MORE_THAN_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0'

ELSIF(A(0)<B(0))THEN

OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA_EQUAL_B<='0'

ELSE

——如果输入中两个数相等的标志位为0，则表明高位不相等，停止比较，输出结果。

OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='0'OA_EQUAL_B<='1'

END IF

ELSE

OA_MORE_THAN_B<=IA_MORE_THAN_BOB_MORE_THAN_A<=IB_MORE_THAN_A

OA_EQUAL_B<=IA_EQUAL_B

END IF

END PROCESS

END BEHAV

VHDL 的英文全名是VHSIC Hardware Description Language(VHSIC硬件描述语言)。VHSIC是Very High Speed Integrated Circuit的缩写，是20世纪80年代在美国国防部的资助下始创的，并最终导致了VHDL语言的出现。1987 年底，VHDL被 IEEE 和美国国防部确认为标准硬件描述语言。VHDL主要用于描述数字系统的结构，行为，功能和接口。除了含有许多具有硬件特征的语句外，VHDL的语言形式和描述风格与句法是十分类似于一般的计算机高级语言。VHDL的程序结构特点是将一项工程设计，或称设计实体（可以是一个元件，一个电路模块或一个系统）分成外部（或称可视部分，及端口）和内部（或称不可视部分），既涉及实体的内部功能和算法完成部分。在对一个设计实体定义了外部界面后，一旦其内部开发完成后，其他的设计就可以直接调用这个实体。这种将设计实体分成内外部分的概念是VHDL系统设计的基本点。

LIBRARY ieee

USE ieee.std_logic_1164.ALL

USE ieee.std_logic_unsigned.ALL

ENTITY cnt16 IS

PORT ( clk : IN std_logic

rst: IN std_logic

en: IN std_logic

cout : OUT std_logic )

END cnt16

ARCHITECTURE behav OF cnt16 IS

signal bcd :std_logic_vector(3 DOWNTO 0)

BEGIN

PROCESS(clk, rst, en)

VARIABLE cqi : std_logic_vector(3 DOWNTO 0)

BEGIN

IF rst = '1' THEN cqi := (OTHERS =>'0')

ELSIF clk'event AND clk='1' THEN

IF en = '1' THEN

IF cqi = "1111" THEN cqi :="0000"

ELSE cqi := cqi + 1

END IF

END IF

END IF

IF cqi = "1111" THEN cout <= '1'

ELSEcout <= '0'

END IF

bcd<=cqi

END PROCESS

END

10110101序列信号发生器.vhd library IEEE use IEEE.std_logic_1164.all use ieee.std_logic_unsigned.all entity count8 is port ( r: in std_logic clk: in STD_LOGIC cout: out std_logic ) end count8 architecture count8_arch of count8 is signal dd: std_logic_vector ( 2 downto 0 ) begin count: process ( r,clk ) begin if ( r='1' ) then dd<="000" elsif( clk'event and clk = '1') then dd <= dd + '1' end if end process count with dd select cout<='1'when"000", '0'when"001", '1'when"010", '1'when"011", '0'when"100", '1'when"101", '0'when"110", '1'when"111", '0'when others

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