程序如下：
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity xuan21 is
Port ( alarm,a,b: in std_logic
y:out std_logic)
end xuan21
architecture one of xuan21 is
begin
process(alarm,a,b)
begin
if alarm='0' then y<=aelse y<=b
end if
end process
end one
仿真波形如下图12：
图12
（2）三位二选一：
模块图如图13。用以进行正常计时时间与闹铃时间显示的选择，alarm输入为按键。当alarm按键未曾按下时二选一选择器会选择输出显示正常的计时结果，否则当alarm按键按下时选择器将选择输出显示闹铃时间显示。
图13
程序如下：
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity x213 is
Port ( alarm : in std_logic
y:out std_logic_vector(3 downto 0)
a,b: in std_logic_vector(3 downto 0))
end x213
architecture one of x213 is
begin
process(alarm,a,b)
begin
if alarm='0' then y<=aelse y<=b
end if
end process
end one
仿真结果如下图14：
图14
8、整点报时及闹时：
模块图如图15。在59分51秒、53秒、55秒、57秒给扬声器赋以低音512Hz信号,在59分59秒给扬声器赋以高音1024Hz信号,音响持续1秒钟,在1024Hz音响结束时刻为整点。当系统时间与闹铃时间相同时给扬声器赋以高音1024Hz信号。闹时时间为一分钟。
图15
程序如下：
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity voice is
Port ( hou1,huo0,min1,min0,sec1,sec0,hh,hl,mh,ml: std_logic_vector(3 downto 0)
in_1000,in_500:in std_logic
q : out std_logic)
end voice
architecture one of voice is
begin
process(min1,min0,sec1,sec0)
begin
if min1="0101" and min0="1001" and sec1="0101" then
if sec0="0001" or sec0="0011" or sec0="0101" or sec0="0111"
then q<=in_500
elsif sec1="0101" and sec0="1001" then q<=in_1000
else q<='0'
end if
else q<='0'
end if
if min1=mh and min0=ml and hou1=hh and huo0=hl then
q<=in_1000
end if
end process
end one
仿真波形如下图16
图16
9、顶层原理图：
三、感想
通过这次设计，既复习了以前所学的知识，也进一步加深了对EDA的了解，让我对它有了更加浓厚的兴趣。特别是当每一个子模块编写调试成功时，心里特别的开心。但是在画顶层原理图时，遇到了不少问题，最大的问题就是根本没有把各个模块的VHD文件以及生成的器件都全部放在顶层文件的文件夹内，还有就是程序设计的时候考虑的不够全面，没有联系着各个模式以及实验板的情况来编写程序，以至于多考虑编写了译码电路而浪费了很多时间。在波形仿真时，也遇到了一点困难,想要的结果不能在波形上得到正确的显示
:在分频模块中，设定输入的时钟信号后，却只有二分频的结果，其余三个分频始终没反应。后来，在数十次的调试之后，才发现是因为规定的信号量范围太大且信号的初始值随机，从而不能得到所要的结果。还有的仿真图根本就不出波形，怎么调节都不管用，后来才知道原来是路径不正确，路径中不可以有汉字。真是细节决定成败啊！总的来说，这次设计的数字钟还是比较成功的，有点小小的成就感，终于觉得平时所学的知识有了实用的价值，达到了理论与实际相结合的目的，不仅学到了不少知识，而且锻炼了自己的能力，使自己对以后的路有了更加清楚的认识，同时，对未来有了更多的信心。
四、参考资料：
1、潘松，王国栋，VHDL实用教程〔M〕.成都:电子科技大学出版社，2000.(1)
2、崔建明主编，电工电子EDA仿真技术北京：高等教育出版社，2004
3、李衍编著，EDA技术入门与提高王行西安：西安电子科技大学出版社，2005
4、侯继红,李向东主编，EDA实用技术教程北京：中国电力出版社，2004
5、沈明山编著，EDA技术及可编程器件应用实训北京：科学出版社，2004
6、侯伯亨等，VHDL硬件描述语言与数字逻辑电路设计西安: 西安电子科技大学出版社，1997
7、辛春艳编著，VHDL硬件描述语言北京：国防工业出版社，2002 就这些
源代码如下 自己把各个模块打好包 下面有个图 自己看看
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY TZKZQ IS
PORT(KEY: IN STD_LOGIC_VECTOR(1 DOWNTO 0) --按键信号
CLK_KEY: IN STD_LOGIC --键盘扫描信号
MAX_DAYS:IN STD_LOGIC_VECTOR(4 DOWNTO 0) --本月最大天数
SEC_EN,MIN_EN,HOUR_EN,DAY_EN,MON_EN,YEAR_EN,WEEK_EN:OUT STD_LOGIC --异步并行置位使能
HOUR_CUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0)
MIN_CUR,SEC_CUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0)
YEAR_CUR:IN STD_LOGIC_VECTOR(6 DOWNTO 0)
MON_CUR :IN STD_LOGIC_VECTOR(3 DOWNTO 0)
DAY_CUR :IN STD_LOGIC_VECTOR(4 DOWNTO 0)
WEEK_CUR:IN STD_LOGIC_VECTOR(2 DOWNTO 0)
SEC,MIN:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0)
HOUR:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)
DAY :BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)
MON :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)
YEAR:BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0)
WEEK:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0))
END ENTITY TZKZQ
ARCHITECTURE ART OF TZKZQ IS
TYPE STATETYPE IS (NORMAL,SEC_SET,MIN_SET,HOUR_SET,DAY_SET,MON_SET,
YEAR_SET,WEEK_SET)
SIGNAL MODE:STATETYPE
BEGIN
PROCESS(KEY,CLK_KEY)
BEGIN
IF CLK_KEY'EVENT AND CLK_KEY='1' THEN
IF KEY="01" THEN
SEC_EN<='1'MIN_EN<='1'HOUR_EN<='1'
DAY_EN<='1'MON_EN<='1'YEAR_EN<='1'
WEEK_EN<='1'
CASE MODE IS
WHEN NORMAL => MODE<=SEC_SETSEC<=SEC_CURSEC_EN<='0'
WHEN SEC_SET => MODE<=MIN_SETMIN<=MIN_CURSEC_EN<='1'MIN_EN<='0'
WHEN MIN_SET => MODE<=HOUR_SETHOUR<=HOUR_CURMIN_EN<='1'HOUR_EN<='0'
WHEN HOUR_SET=> MODE<=DAY_SETDAY<=DAY_CURHOUR_EN<='1'DAY_EN<='0'
WHEN DAY_SET => MODE<=MON_SETMON<=MON_CURDAY_EN<='1'MON_EN<='0'
WHEN MON_SET => MODE<=YEAR_SETYEAR<=YEAR_CUR MON_EN<='1'
YEAR_EN<='0'
WHEN YEAR_SET => MODE<=WEEK_SETWEEK<=WEEK_CURYEAR_EN<='1'WEEK_EN<='0'
WHEN WEEK_SET => MODE<=NORMAL
END CASE
ELSIF KEY="10" THEN --如果按下调整键，则自加
CASE MODE IS
WHEN SEC_SET => SEC_EN<='0'
--异步并行置位使能有效
IF SEC="111011" THEN SEC<="000000"
--如果秒计数到59，返回到0重新计数
ELSE SEC<=SEC+1 --否则继续计数
END IF
WHEN MIN_SET => MIN_EN<='0'
IF MIN="111011" THEN MIN<="000000"
ELSE MIN<=MIN+1
END IF
WHEN HOUR_SET=> HOUR_EN<='0'
IF HOUR="11000" THEN HOUR<="00000"
ELSE HOUR<=HOUR+1
END IF
WHEN DAY_SET => DAY_EN<='0'
IF DAY=MAX_DAYS THEN DAY<="00001"
ELSE DAY<=DAY+1
END IF
WHEN WEEK_SET=> WEEK_EN<='0'
IF WEEK="111" THEN WEEK<="001"
ELSE WEEK<=WEEK+1
END IF
WHEN OTHERS=>NULL
END CASE
END IF
END IF
END PROCESS
END ARCHITECTURE ART
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CNT60 IS
PORT(LD: IN STD_LOGIC
CLK: IN STD_LOGIC
DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0)
NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0)
CO: OUT STD_LOGIC)
END ENTITY CNT60
ARCHITECTURE ART OF CNT60 IS
BEGIN
PROCESS(CLK,LD) IS
BEGIN
IF(LD='0') THEN
NUM<=DATA
ELSIF CLK'EVENT AND CLK='1' THEN
IF NUM="111011" THEN --59
NUM<="000000"CO<='1'
ELSE
NUM<=NUM+1CO<='0'
END IF
END IF
END PROCESS
END ARCHITECTURE ART
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CNT60 IS
PORT(LD: IN STD_LOGIC
CLK: IN STD_LOGIC
DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0)
NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0)
CO: OUT STD_LOGIC)
END ENTITY CNT60
ARCHITECTURE ART OF CNT60 IS
BEGIN
PROCESS(CLK,LD) IS
BEGIN
IF(LD='0') THEN
NUM<=DATA
ELSIF CLK'EVENT AND CLK='1' THEN
IF NUM="111011" THEN --59
NUM<="000000"CO<='1'
ELSE
NUM<=NUM+1CO<='0'
END IF
END IF
END PROCESS
END ARCHITECTURE ART
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CNT24 IS
PORT(LD: IN STD_LOGIC
CLK: IN STD_LOGIC
DATA: IN STD_LOGIC_VECTOR(4 DOWNTO 0)
NUM: BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)
CO: OUT STD_LOGIC)
END ENTITY CNT24
ARCHITECTURE ART OF CNT24 IS
BEGIN
PROCESS(CLK,LD) IS
BEGIN
IF(LD='0') THEN
NUM<=DATA
ELSIF CLK'EVENT AND CLK='1' THEN
IF NUM="11000" THEN --24
NUM<="00000"CO<='1'
ELSE
NUM<=NUM+1CO<='0'
END IF
END IF
END PROCESS
END ARCHITECTURE ART
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CNT30 IS
PORT(LD:IN STD_LOGIC
CLK:IN STD_LOGIC
NIAN:IN STD_LOGIC_VECTOR(6 DOWNTO 0)
YUE :IN STD_LOGIC_VECTOR(3 DOWNTO 0)
DATA:IN STD_LOGIC_VECTOR(4 DOWNTO 0)
NUM:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)
MAX_DAYS:OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
CO:OUT STD_LOGIC)
END ENTITY CNT30
ARCHITECTURE ART OF CNT30 IS
SIGNAL TOTAL_DAYS:STD_LOGIC_VECTOR(4 DOWNTO 0)
BEGIN
PROCESS(CLK,LD) IS
VARIABLE IS_RUNNIAN:STD_LOGIC
BEGIN
CASE NIAN IS
WHEN "0000000" => IS_RUNNIAN:='1' --0
WHEN "0000100" => IS_RUNNIAN:='1' --4
WHEN "0001000" => IS_RUNNIAN:='1' --8
WHEN "0001100" => IS_RUNNIAN:='1' --12
WHEN "0010000" => IS_RUNNIAN:='1' --16
WHEN "0010100" => IS_RUNNIAN:='1' --20
WHEN "0011000" => IS_RUNNIAN:='1' --24
WHEN "0011100" => IS_RUNNIAN:='1' --28
WHEN "0100000" => IS_RUNNIAN:='1' --32
WHEN "0100100" => IS_RUNNIAN:='1' --36
WHEN "0101000" => IS_RUNNIAN:='1' --40
WHEN "0101100" => IS_RUNNIAN:='1' --44
WHEN "0110000" => IS_RUNNIAN:='1' --48
WHEN "0110100" => IS_RUNNIAN:='1' --52
WHEN "0111000" => IS_RUNNIAN:='1' --56
WHEN "0111100" => IS_RUNNIAN:='1' --60
WHEN "1000000" => IS_RUNNIAN:='1' --64
WHEN "1000100" => IS_RUNNIAN:='1' --68
WHEN "1001000" => IS_RUNNIAN:='1' --72
WHEN "1001100" => IS_RUNNIAN:='1' --76
WHEN "1010000" => IS_RUNNIAN:='1' --80
WHEN "1010100" => IS_RUNNIAN:='1' --84
WHEN "1011000" => IS_RUNNIAN:='1' --88
WHEN "1011100" => IS_RUNNIAN:='1' --92
WHEN "1100000" => IS_RUNNIAN:='1' --96
WHEN OTHERS => IS_RUNNIAN:='0'
END CASE
CASE YUE IS
WHEN "0001" => TOTAL_DAYS<="11111" --1
WHEN "0011" => TOTAL_DAYS<="11111" --3
WHEN "0101" => TOTAL_DAYS<="11111" --5
WHEN "0111" => TOTAL_DAYS<="11111" --7
WHEN "1000" => TOTAL_DAYS<="11111" --8
WHEN "1010" => TOTAL_DAYS<="11111" --10
WHEN "1100" => TOTAL_DAYS<="11111" --12
WHEN "0100" => TOTAL_DAYS<="11110" --4
WHEN "0110" => TOTAL_DAYS<="11110" --6
WHEN "1001" => TOTAL_DAYS<="11110" --9
WHEN "1011" => TOTAL_DAYS<="11110" --11
WHEN "0010" =>
IF (IS_RUNNIAN='1') THEN
TOTAL_DAYS<="11101"
ELSE
TOTAL_DAYS<="11100"
END IF
WHEN OTHERS=>NULL
END CASE
IF(LD='0') THEN
NUM<=DATA
ELSIF CLK'EVENT AND CLK='1' THEN
MAX_DAYS<=TOTAL_DAYS
IF NUM=TOTAL_DAYS THEN --99
NUM<="00001"CO<='1'
ELSE
NUM<=NUM+1CO<='0'
END IF
END IF
END PROCESS
END ARCHITECTURE ART
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CNT7 IS
PORT(LD: IN STD_LOGIC
CLK: IN STD_LOGIC
DATA: IN STD_LOGIC_VECTOR(2 DOWNTO 0)
NUM: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0))
END ENTITY CNT7
ARCHITECTURE ART OF CNT7 IS
BEGIN
PROCESS(CLK,LD) IS
BEGIN
IF(LD='0') THEN
NUM<=DATA
ELSIF CLK'EVENT AND CLK='1' THEN
IF NUM="111" THEN --7
NUM<="000"
ELSE
NUM<=NUM+1
END IF
END IF
END PROCESS
END ARCHITECTURE ART
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CNT12 IS
PORT(LD: IN STD_LOGIC
CLK: IN STD_LOGIC
DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0)
NUM: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)
CO: OUT STD_LOGIC)
END ENTITY CNT12
ARCHITECTURE ART OF CNT12 IS
BEGIN
PROCESS(CLK,LD) IS
BEGIN
IF(LD='0') THEN
NUM<=DATA
ELSIF CLK'EVENT AND CLK='1' THEN
IF NUM="1100" THEN --12
NUM<="0000"CO<='1'
ELSE
NUM<=NUM+1CO<='0'
END IF
END IF
END PROCESS
END ARCHITECTURE ART
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CNT99 IS
PORT(LD: IN STD_LOGIC
CLK: IN STD_LOGIC
DATA: IN STD_LOGIC_VECTOR(6 DOWNTO 0)
NUM: BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0))
END ENTITY CNT99
ARCHITECTURE ART OF CNT99 IS
BEGIN
PROCESS(CLK,LD) IS
BEGIN
IF(LD='0') THEN
NUM<=DATA
ELSIF CLK'EVENT AND CLK='1' THEN
IF NUM="1100011" THEN --12
NUM<="0000000"
ELSE
NUM<=NUM+1
END IF
END IF
END PROCESS
END ARCHITECTURE ART
欢迎分享，转载请注明来源：内存溢出
微信扫一扫
支付宝扫一扫
评论列表（0条）