急！！哪位高手有VHDL语言的倍频器代码？是倍频哦！详细点的！

use IEEE.STD_LOGIC_1164.ALL

use IEEE.STD_LOGIC_ARITH.ALL

use IEEE.STD_LOGIC_UNSIGNED.ALL

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM

--use UNISIM.VComponents.all

entity minutes is

Port ( rst3,selector2,ky_2j : in STD_LOGIC

B10 : in std_logic

C : out std_logic

dat30 : out std_logic_vector(7 downto 0))

end minutes

architecture Behavioral of minutes is

signal dat31,dat32 : std_logic_vector(7 downto 0):=(others =>'0')

begin

process(rst3,B10,ky_2j)

begin

case selector2 is

when '1' =>dat32<=dat31if ky_2j'闷游event and ky_2j='1' then

if dat31(7 downto 4)="0101" and dat31(3 downto 0)="1001"

then dat31(7 downto 0)<="00000000"

elsif dat31(3 downto 0)<"1001" then dat31(3 downto 0)<=dat31(3 downto 0)+1

else dat31(3 downto 0)<="0000"

if dat31(7 downto 4)<"0101" then dat31(7 downto 4)<=dat31(7 downto 4)+1

else dat31(7 downto 4)<="0000"

end if

end if

end if

dat30<=dat31

when '0' =>dat31<=dat32if(rst3 = '0') then dat32<=(others =>'0')

elsif B10'event and B10='1'蚂茄销 then

if dat32(7 downto 4)="0101" and dat32(3 downto 0)="1001"

then C<='1'dat32(7 downto 0)<="00000000"

else C<='纳团0'

if dat32(3 downto 0)<"1001" then dat32(3 downto 0)<=dat32(3 downto 0)+1

else dat32(3 downto 0)<="0000"

if dat32(7 downto 4)<"0101" then dat32(7 downto 4)<=dat32(7 downto 4)+1

else dat32(7 downto 4)<="0000"

end if

end if

end if

end if

dat30<=dat32

when others =>null

end case

end process

end Behavioral

你把temp定义为variable,并把"temp<="改为谈掘temp:=试一下，（注意variable的定义位置是在进程中,而不是在结构体中） 是varialbe时才时立即赋值

是signal时含拍核是延时赋值，也就是说贺返temp<=temp+1，temp的值并不是马上加一，而要等到下次进程执行时（下一个上升沿），它的值才会加一 ,所以在第四个上升沿时，temp的值始终是第三个上升沿的值2