eda中三输入一输出的程序怎么写？

ENTITY triple IS

PORT(a,b,c: IN bit

outa,outb,outc: OUT bit)

END

ARCHITECTURE rtl OF triple IS

BEGIN

outa <空慧坦斗桐碧饥= a

outb <= NOT b

outc <= a OR b OR c

END

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

entity v1206 is

port(RST,EN,T : in std_logic

a,b : in std_logic_vector(3 downto 0)

y0,y1 : out std_logic_vector(3 downto 0))

end v1206

architecture one of v1206 is

begin

process(RST,EN,T,a,b)

begin

if RST='0' then

y0 <= "0000"

y1 <= "0000"消和

else if EN='1'橡帆 then

if T='梁桥雹0' then

y0 <= a-b+a

else

y1 <= b(2 downto 0)&b(3)

end if

end if

end if

end process

end one

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