VHDL语言设计一个6输入或非门

ENTITY nor6 IS

PORT ( a,b,c,d,e,f: IN bit

y: OUT bit)

END

ARCHITECTURE rtl OF nor6 IS

BEGIN

y <= NOT(a OR b OR c OR d OR e OR f)

END

ENTITY adder IS

PORT(a,b,c: IN bit

s,c0: OUT bit)

END adder

ARCHITECTURE one OF adder IS

SIGNAL y_n:bit_vector(7 DOWNTO 0)

BEGIN

decoder:PROCESS(a,b,c)

VARIABLE y:bit_vector(7 DOWNTO 0)

BEGIN

y := (OTHERS =>'1'罩迹侍)

CASE c&b&a IS

WHEN "000" =>y(0) := '0'

WHEN "001" =>y(1) := '0'

WHEN "010" =>y(2) := '0'

WHEN "011"物吵 =>y(3) := '0'

WHEN "100" =>y(4) := '0'

WHEN "101" =>y(5) := '0'

WHEN "110" =>y(6) := '0'州信

WHEN "111" =>y(7) := '0'

END CASE

y_n <= y

END PROCESS

s <= NOT(y_n(1) AND y_n(2) AND y_n(4) AND y_n(7))

c0 <= NOT(y_n(3) AND y_n(5) AND y_n(6) AND y_n(7))

END one

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