请帮忙设计一个分频器，用VHDL语言写的。100kHz的信号分成40khz

要多少分频 就改 IF TEMP1=1000 THEN 里面1000这个数据就可以了 要注意不要超出数据长度了就可以 如果超出了就可以2次或者多次分频 都可以改1000 这个数据就可以

而且等于1000是2000分频器 依此类推

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

ENTITY FENP IS

PORT(CLK:IN BIT;

CLK1:BUFFER BIT);

END ENTITY;

ARCHITECTURE OO OF FENP IS

BEGIN

PROCESS(CLK)

VARIABLE TEMP1: NATURAL;

BEGIN

IF CLK'EVENT AND CLK='1' THEN

TEMP1:=TEMP1+1;

IF TEMP1=1000 THEN

TEMP1:=0;

CLK1<=NOT CLK1;

END IF;

END IF;

END PROCESS;

END;

clk 输入一个相对较大的频率,

频率要多少就用N_diviseur除!

LIBRARY IEEE;

USE IEEEStd_Logic_1164ALL;

ENTITY div IS

GENERIC( n_diviseur : INTEGER := 2 );

PORT ( clk : IN Std_Logic;

clock : OUT Std_Logic);

END ENTITY;

ARCHITECTURE beha OF div IS

BEGIN

PROCESS (clk)

VARIABLE compteur : INTEGER RANGE 0 TO n_diviseur;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF (compteur >= n_diviseur-1) THEN

compteur := 0;

clock <= '1';

ELSE

compteur := compteur + 1;

clock <= '0';

END IF;

END IF;

END PROCESS;

END ARCHITECTURE;

这样不行的，这样不能奇数分频。（奇数分频是要先倍频再分频的，比如3分频的话是要先2倍频再6分频。那样的话，新的时钟的脉冲沿不是在原时钟的触发沿处，而是在电平中变化的。）再说，你前面的IF语句也有错误，是产生歧义了。

下面我给你个任意分频程序吧！

VHDL的任意整数且占空比为50%分频代码

说明如下：

1其中top file 为 division，其中的clk_com是比较的频率，用它来和分频后波形进行比较，便于观察，

2any_enve为任意偶数分频文件

3any_odd为任意奇数分频文件

4是一个用于2进制与8进制的译码器，我用它来显示在数码管上当前到底是多少分频

5以下代码在开发板上实验过，请大家放心使用，欢迎转载，但请注明出处，另外说明由于用的是quartus71编辑的，中间无法加中文注释，请大家慢慢读了；以下是代码：

------the top file of the design division

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_arithall;

use ieeestd_logic_unsignedall;

entity division is

port (input : in std_logic_vector(7 downto 0);

clk : in std_logic;

clk_out : out std_logic;

clk_com : out std_logic;

led1: out std_logic_vector(6 downto 0);

led2: out std_logic_vector(6 downto 0);

led3: out std_logic_vector(6 downto 0));

end entity division;

--------------------------------------------------

architecture freq of division is

component decoder is----decoder

port(bin : in std_logic_vector(2 downto 0);

de : out std_logic_vector(6 downto 0));

end component;

component any_even is----any_even division

generic (data_width : integer := 8 );

port(input1 : in std_logic_vector(data_width-1 downto 0);

clk_in : in std_logic;

clk_out : out std_logic);

end component any_even;

component any_odd is-----any_even division

generic (data_width : integer := 8);

port(input2 : in std_logic_vector(data_width - 1 downto 0);

clk_in : in std_logic;

clk_out : out std_logic);

end component any_odd;

signal temp1,temp2 : std_logic;

begin

u1: decoder port map(bin=>input(2)&input(1)&input(0),de=>led1);

u2: decoder port map(bin=>input(5)&input(4)&input(3),de=>led2);

u3: decoder port map(bin=>'0'&input(7)&input(6),de=>led3);

u4: any_even port map(input,clk,temp1);

U5: any_odd port map(input,clk,temp2);

process(clk,input)

begin

if input(0)= '0' then

clk_out <= temp1;

else clk_out <= temp2;

end if;

end process;

clk_com <= clk;

end architecture freq;

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_arithall;

use ieeestd_logic_unsignedall;

entity any_even is

generic (data_width : integer := 8 );

port(input1 : in std_logic_vector(data_width-1 downto 0);

clk_in : in std_logic;

clk_out : out std_logic);

end entity any_even;

architecture div1 of any_even is

signal clk_outQ : std_logic ;

signal coutQ : std_logic_vector (data_width - 1 downto 0);

begin

-------------------------------------------------

process(clk_in)

begin

if clk_in'event and clk_in = '1' then

if coutQ < (conv_integer(input1) - 1) then

coutQ <= coutQ + 1;

else coutQ <= (others => '0');

end if;

end if;

end process;

---------------------------------------------------

process(coutQ)

begin

if coutQ < (conv_integer(input1))/2 then

clk_outQ <= '0';

else clk_outQ <= '1';

end if;

end process;

clk_out <= clk_outQ;

end architecture div1;

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_unsignedall;

use ieeestd_logic_arithall;

entity any_odd is

generic (data_width : integer := 8);

port(input2 : in std_logic_vector(data_width - 1 downto 0);

clk_in : in std_logic;

clk_out : out std_logic);

end entity any_odd;

architecture div2 of any_odd is

signal cout1,cout2 : std_logic_vector(data_width - 1 downto 0);

signal clk1,clk2 : std_logic;

begin

process(clk_in)------rising edge

begin

if clk_in'event and clk_in='1' then

if cout1 < (conv_integer(input2)-1) then

cout1 <= cout1 + 1;

else cout1 <= (others => '0');

end if;

if cout1 < (conv_integer(input2)-1)/2 then

clk1 <= '1';

else clk1 <= '0';

end if;

end if;

end process;

---------------------------

process(clk_in)------falling edge

begin

if clk_in'event and clk_in='0' then

if cout2 < (conv_integer(input2)-1) then

cout2 <= cout2 + 1;

else cout2 <= (others => '0');

end if;

if cout2 < (conv_integer(input2)-1)/2 then

clk2 <= '1';

else clk2 <= '0';

end if;

end if;

end process;

clk_out <= clk1 or clk2;

end architecture div2;

library ieee;

use ieeestd_logic_1164all;

entity decoder is

port(bin : in std_logic_vector(2 downto 0);

de : out std_logic_vector(6 downto 0));

end entity;

----------------------------------------------------

architecture deco of decoder is

begin

process(bin)

begin

case bin is

when "000" => de <= "0111111";---0

when "001" => de <= "0000110";---1

when "010" => de <= "1011011";---2

when "011" => de <= "1001111";---3

when "100" => de <= "1100110";---4

when "101" => de <= "1101101";---5

when "110" => de <= "1111101";---6

when others => de <= "0000111";---7

end case;

end process;

end architecture;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_ARITHALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY fq_divider IS

generic(n:integer:=60000);

PORT(

CLK,reset: IN STD_LOGIC;

CLK_OUT:buffer STD_LOGIC

);

END;

ARCHITECTURE A OF fq_divider IS

SIGNAL CNT1,CNT2:integer:=0;

SIGNAL OUTTEMP:STD_LOGIC;

SIGNAL LOUT:STD_LOGIC;

SIGNAL OUT3:STD_LOGIC:='0';

BEGIN

P1:PROCESS(CLK)

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CNT1=n-1 THEN

CNT1<=0;

ELSE

CNT1<=CNT1+1;

END IF;

END IF;

END PROCESS P1;

P2:PROCESS(CLK)

BEGIN

IF CLK'EVENT AND CLK='0' THEN

IF CNT2=n-1 THEN

CNT2<=0;

ELSE

CNT2<=CNT2+1;

END IF;

END IF;

END PROCESS P2;

P3:PROCESS(CNT1,CNT2 )

BEGIN

if ((n mod 2)=1) then

IF CNT1=1 THEN

IF CNT2=0 THEN

OUTTEMP<='1';

ELSE

OUTTEMP<='0';

END IF;

ELSIF CNT1=(n+1)/2 THEN

IF CNT2=(n+1)/2 THEN

OUTTEMP<='1';

ELSE OUTTEMP<='0';

END IF;

ELSE

OUTTEMP<='0';

END IF;

else

if cnt1=1 then

outtemp<='1';

elsif (cnt1=(n/2+1)) then

outtemp<='1';

else

outtemp<='0';

end if;

end if;

END PROCESS P3;

P4:PROCESS(OUTTEMP,clk,reset)

BEGIN

if reset='0' then

clk_out<=clk;

elsif ((n/=2) and (n/=1)) then

IF OUTTEMP'EVENT AND OUTTEMP='1' THEN

CLK_OUT<=NOT CLK_OUT;

END IF;

elsif (n=2) then

if(clk'event and clk='1')then

clk_out<=not clk_out;

end if;

else

clk_out<=clk;

end if;

END PROCESS P4;

END A;

能否告知系统提示的错误是什么？可能是你的FULL定义成变量的形式，对变量的赋值应该用“：=”而你最后倒数第四和第五句程序都是用的信号赋值方式“<=”。还有就是你的FULL没有赋初值。

以上就是关于请帮忙设计一个分频器，用VHDL语言写的。100kHz的信号分成40khz全部的内容，包括:请帮忙设计一个分频器，用VHDL语言写的。100kHz的信号分成40khz、用VHDL编写一个分频器,实现输出1MHz-1Hz之间的任意频率、高分：用VHDL语言编写的一个整数分频器有点问题等相关内容解答，如果想了解更多相关内容，可以关注我们，你们的支持是我们更新的动力！