我写的Verilog 程序，出现一些问题，求大神解决

always @(posedge clk or con or cnt1 or negedge rst) 这句改成always @(posedge clk or negedge rst)

module traffic(clk,urgency,east_west,south_north,led);

input clk;

input urgency;

output [7:0]east_west,south_north;

output [5:0]led;

reg [7:0]east_west,south_north;

reg [5:0]led;

initial begin

east_west<=8'b0;

south_north<=8'b0;

led<=6'b100001;end

always @(posedge clk)

begin if(urgency==1) led<=6'b100100;

else if(east_west==8'b0 && south_north==8'b0) begin

east_west<=8'b00101101;

south_north<=8'b00101000;

led<=6'b100001;end

else if(east_west==8'b00000110 && south_north==8'b1) begin

east_west<=8'b00000101;

south_north<=8'b00000101;

led<=6'b100010; end

else if(east_west==8'b1 && south_north==8'b1 && led[5]==1'b1) begin

east_west<=8'b00101000;

south_north<=8'b00101101;

led<=6'b001100; end

else if(east_west==8'b1 && south_north==8'b00000110) begin

east_west<=8'b00000101;

south_north<=8'b00000101;

led<=6'b010100;end

else if(east_west==8'b1 && south_north==8'b1 && led[2]==1'b1) begin

east_west<=8'b00101101;

south_north<=8'b00101000;

led<=6'b100001; end

else if(east_west[3:0]==4'b0000) begin

east_west<=east_west-8'b111;

south_north<=south_north-1'b1; end

else if(south_north[3:0]==4'b0000) begin

east_west<=east_west-1'b1;

south_north<=south_north-8'b111; end

else begin

east_west<=east_west-1'b1;

south_north<=south_north-1'b1;

end

end

endmodule

上面是我前一段时间写的交通灯控制器设计代码，相应的英文字母对应相应的信号

几个LED，用不了嫩长的程序吧

module ledwater (clk_50M,dataout);

input clk_50M; //系统时钟50M输入 从12脚输入。

output [7:0] dataout; //我们这里用12个LED灯，

reg [7:0] dataout;

reg [27:0] count; //分频计数器

//分频计数器

always @ ( posedge clk_50M )

begin

count<=count+1;

end

always @ ( count[27:24] )

begin

case ( count[27:24] )

// case ( count[27:24] )这一句希望初学者看明白,

// 也是分频的丶 // 只有在0的那一位 对应的LED灯才亮。

0: dataout<=8'b11111110;

1: dataout<=8'b11111101;

2: dataout<=8'b11111011;

3: dataout<=8'b11110111;

4: dataout<=8'b11101111;

5: dataout<=8'b11011111;

6: dataout<=8'b10111111;

7: dataout<=8'b01111111;

8: dataout<=8'b11111111;

9: dataout<=8'b01111111;

10: dataout<=8'b10111111;

11: dataout<=8'b11011111;

12: dataout<=8'b11101111;

13: dataout<=8'b11110111;

14: dataout<=8'b11111011;

15: dataout<=8'b11111101;

endcase

end

endmodule

// FPGA程序里面要避免用复杂的运算

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