用VHDL语言设计一个具有清零,使能,置数的4位二进制加减法计数器的源程序,谢谢

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

entity counter4 is

port

(

clk : in std_logic;

load : in std_logic;

clr : in std_logic;

up_down: in std_logic;

DIN : in std_logic_vector(3 downto 0);

DOUT : out std_logic_vector(3 downto 0);

c : out std_logic

);

end counter4;

architecture rt1 of counter4 is

signal clk_1Hz:std_logic;

signal data_r:std_logic_vector(3 downto 0);

component frediv

port

(

clk :in std_logic;

clkout:out std_logic

);

end component;

begin

U1:frediv port map(clk,clk_1Hz);

DOUT <= data_r;

process(clk_1Hz,load,clr,up_down,DIN)

begin

if clr = '1' then

data_r <= "0000";

elsif load = '1' then

data_r <= DIN;

else if clk_1Hz'event and clk_1Hz = '1' then

if up_down = '1' then

if data_r = "1111" then

c <= '0';

data_r <= "0000";

else

data_r <= data_r + 1;

c<= '1';

end if;

else

if data_r = "0000" then

c <= '0';

data_r <= "1111";

else

data_r <= data_r - 1;

c<= '1';

end if;

end if;

end if;

end if;

end process;

end rt1;

LIBRARY ieee;

USE ieeestd_logic_1164ALL;

USE ieeestd_logic_unsignedALL;

ENTITY cnt16 IS

PORT ( clk : IN std_logic;

rst: IN std_logic;

en: IN std_logic;

cout : OUT std_logic );

END cnt16;

ARCHITECTURE behav OF cnt16 IS

signal bcd :std_logic_vector(3 DOWNTO 0);

BEGIN

PROCESS(clk, rst, en)

VARIABLE cqi : std_logic_vector(3 DOWNTO 0);

BEGIN

IF rst = '1' THEN cqi := (OTHERS =>'0') ;

ELSIF clk'event AND clk='1' THEN

IF en = '1' THEN

IF cqi = "1111" THEN cqi :="0000";

ELSE cqi := cqi + 1;

END IF;

END IF;

END IF;

IF cqi = "1111" THEN cout <= '1';

ELSE cout <= '0';

END IF;

bcd<=cqi;

END PROCESS;

END;

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