library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
entity shicount is
port(clk,reset,enable: in std_logic
a,b,c,d,e,f,g: out std_logic
tp : out std_logic_vector(0 to 3)
xian: out std_logic_vector(0 to 6)
count :out std_logic)
end shicount
architecture xu of shicount is
signal temp :std_logic_vector(0 to 3)
signal xianshi:std_logic_vector(0 to 6)
begin
process(clk,reset,enable)
begin
if (reset='1')then temp<="0000"
elsif (enable='1') then
if (clk' event and clk='1')
then if (temp<="1000") then temp<=temp+1
else temp<="0000"
end if
end if
end if
end process
process(temp)
begin
case temp is
when "0000"=> xianshi<="0000001"count<='0'
when "0001"=> xianshi<="0110000"count<='0'
when "0010"=> xianshi<="1101101"count<='0'
when "0011"=> xianshi<="1111001"count<='0'
when "0100"=> xianshi<="0110011"count<='0'
when "0101"=> xianshi<="1011011"count<='0'
when "0110"=> xianshi<="0011111"count<='0'
when "0111"=> xianshi<="1110000"count<='0'
when "1000"=> xianshi<="1111111"count<='0'
when "1001"=> xianshi<="1110011"count<='1'
when others=> xianshi<="0000000"count<='0'
end case
end process
a<=xianshi(6) b<=xianshi(5) c<=xianshi(4) d<=xianshi(3)
e<=xianshi(2)f<=xianshi(1) g<=xianshi(0) tp<=temp
xian<=xianshi
end xu
eda编程9人表决器程序详解://本程序用VERILOG HDL语言实现,描述9人表决器。
module biaojueqi(vote,ledr,ledg,dis_out)
input [8:0] vote
reg [6:0] dis_out
integer i,sum//sum表示赞同的人数
for(i=0i<=8i=i+1)
if(vote[i]) sum<=sum+1
end
always @(sum) //结果由dis_out显示在数码管上
case (sum)
0: dis_out[6:0]<=7'b1111110
1: dis_out[6:0]<=7'b0110000
2: dis_out[6:0]<=7'b1101101
3: dis_out[6:0]<=7'b1111001
4: dis_out[6:0]<=7'b0110011
5: dis_out[6:0]<=7'b1011011
6: dis_out[6:0]<=7'b1011111
7: dis_out[6:0]<=7'b1110000
8: dis_out[6:0]<=7'b1111111
9: dis_out[6:0]<=7'b1111011
endmodule
内容简介
本书从实际应用的角度出发,全面系统地介绍了EDA技术和硬件描述语言VHDL,将VHDL的基础知识、编程技巧、实用方法与实际工程开发技术在EDA软件设计平台上很好地结合起来,使读者能够通过本书的学习迅速了解并掌握EDA技术的基本理论和工程开发实用技术。
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