一位十进制加法计数器的怎么用VHDL语言实现

十进制加法器的VHDL程序及注释如下：

// 包含所需的库

library IEEE

use IEEE.std_logic_1164.all

use IEEE.std_logic_unsigned.all

// 定义所需的输入输出端口和寄存器

ENTITY BCD_counter IS

 PORT(clr,clk: IN std_logic

 BCD_q:OUT std_logic_vector(3 DOWNTO 0))

END BCD_counter

ARCHITECTURE behavioral OF BCD_counter IS

 SIGNAL counter:std_logic_vector(3 DOWNTO 0)

BEGIN

 process(CLR,CLK)

 begin

 IF clr='0' then  // 清零标志有效，则计数器清零

     counter <= (OTHERS => '0')

 ELSIF rising_edge(clk) THEN

     IF counter < "1001" THEN     // 计数器数值小于10，计数器加1

 袜咐        counter 激蔽<= counter +'1'

     ELSE counter <= (OTHERS => '0') // 计数器数值大于等于10，计数器明好州清零

     END IF

 END IF

 end process

 BCD_q <= counter

END behavioral

一位全加前笑穗慧卜器源代码如升薯下：

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

use ieee.std_logic_arith.all

entity bit1adder is

port(

a,b,ci:in std_logic

s,co:out std_logic

)

end bit1adder

architecture func of bit1adder is

signal:x,y:std_logic

begin

x<=a xor b

y<=x and ci

s<=x xor ci

co<=y or (a and b)

end func

library ieee

use ieee.std_logic_1164.all

entity product_adder_subtracter is

port(

a,b:in std_logic_vector(7 downto 0)

s:out std_logic_vector(8 downto 0))

end

architecture behavioral of product_adder_subtracter is

begin

behavior:process(a,b) is

variable carry_in:std_logic

variable carry_out:std_logic

variable op2:std_logic_vector(b'range)

begin

op2:=b

end if

for index in 0 to 7 loop

carry_in:=carry_out

s(index)<=a(index) xor op2(index)xor carry_in

carry_out:=(a(index)and op2(index))

or(carry_in and (a(index) xor op2(index)))

end loop

s(8)<=a(7) xor op2(7) xor carry_out

end process

end

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