用VHDL编写N分频器

分频没必要一定用锁相环啊，普通分频就可以了啊，锁相环一般是用倍频的，我把代码给你，你研究一下，这个电路我前两天刚调试成功
-----------------------------------------------------------------------
-- This section contains clock manager
-----------------------------------------------------------------------
IBUFG_clock : IBUFG
generic map (
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only)
IOSTANDARD => "DEFAULT")
port map (
O => clkin_buf, -- Clock buffer output
I => clk_in -- Clock buffer input (connect directly to top-level port)
);
BUFG_clk_sys : BUFG
port map (
O =>clk_sys, -- Clock buffer output
I => CLK0 -- Clock buffer input
);
BUFG_clk_fx : BUFG
port map (
O => TX_CLK, -- Clock buffer output
I => CLKFX -- Clock buffer input
);
DCM_gnet : DCM
generic map (
CLKDV_DIVIDE => 80, -- Divide by: 15,20,25,30,35,40,45,50,55,60,65
-- 70,75,80,90,100,110,120,130,140,150 or 160
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 00, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => CLK0, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
CLK2X => CLK2X, -- 2X DCM CLK output --100MHZ
-- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => CLKFX, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
-- LOCKED => LOCKED, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => clk_sys, -- DCM clock feedback
CLKIN => clkin_buf, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => PSCLK, -- Dynamic phase adjust clock input
-- PSEN => '0', -- Dynamic phase adjust enable input
-- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => rst_manu_h -- DCM asynchronous reset input
);
库文件
library IEEE;
Library UNISIM;
use IEEESTD_LOGIC_1164ALL;
use IEEESTD_LOGIC_UNSIGNEDALL;
use IEEESTD_LOGIC_ARITHALL;
use UNISIMvcomponentsall;

1 在ISE项目中打开“view design summary”。
2 在右侧design summary窗口中选择“detailed reports”中的“map report”。
3 出现如下所示的内容。
Design Summary
--------------
Logic Utilization:
1 FPGA资源利用率
Number of Slice Flip Flops: 11,555 out of 178,176 6%
Slice内部FF寄存器利用率：6%
Number of 4 input LUTs: 21,446 out of 178,176 12%
4输入LUT利用率：12%
Logic Distribution:
2 被使用的FPGA资源分布情况
Number of occupied Slices: 16,079 out of 89,088 18%
占用的Slice数目：18%。
假如一个Slice有两个LUT，片内总共有100个单位的Slice， 也即有200个单位的LUT，那么如果我们的设计使用了24个单元的LUT，而这些LUT分布在18个Slice里面时，恰好就是现在的这种情况了。即 Slice利用率18% （18/100），LUT利用率12%（24/200）。
Number of Slices containing only related logic: 16,079 out of 16,079 100%
Slice里面只有互相相关的逻辑，这种Slice所占比例：100%
Number of Slices containing unrelated logic: 0 out of 16,079 0%
Slice里面有互不相关的逻辑，这种Slice所占比例：0%
See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 25,027 out of 178,176 14%
3 4输入LUT的利用率：14%
Number used as logic: 21,446
设计用LUT数目：21446
Number used as a route-thru: 787
布线路由用LUT：787
Number used for Dual Port RAMs: 2,596
双端口RAM用LUT：2596
(Two LUTs used per Dual Port RAM)
每个双端口RAM由两个LUT构成
Number used as 16x1 RAMs: 64
用做16x1RAM的LUT：64
Number used as Shift registers: 134
用做shift register的LUT：134
4 其他
Number of bonded IOBs: 495 out of 960 51%
Number of BUFG/BUFGCTRLs: 8 out of 32 25%
Number used as BUFGs: 8
Number used as BUFGCTRLs: 0
Number of FIFO16/RAMB16s: 19 out of 336 5%
Number used as FIFO16s: 0
Number used as RAMB16s: 19
Number of DCM_ADVs: 2 out of 12 16%
Number of BSCAN_VIRTEX4s: 1 out of 4 25%
Number of RPM macros: 12
5 等效门数
Total equivalent gate count for design: 1,681,068
这是一个168万门的设计。
Additional JTAG gate count for IOBs: 23,760
6 等效门数的意义
(1) 等效门数是对ASIC实现的大概估计。这里包含了两个意思：一呢是对ASIC实现的估计，也就是说ASIC实现的时候是在168万门左右的数量级；二呢是个大概估计，所以要强调的是等效门数仅供参考，和最后真正的ASIC结果可能会相去甚远，比如可能是100万门，也可能是300万门，甚至无法理解的数目。
(2) 等效门数的单位是二输入的NAND和NOR，这一点未经确认，但是有这样的印象，因为在CMOS工艺里面NAND、NOR、NOT和XOR是基本的门结构。

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