基本组合逻辑功能双向管脚的Verilog HDL源代码

　　电子发烧友网核心提示：本例程是Verilog HDL源代码：关于基本组合逻辑功能中双向管脚的功能实现源代码。
Verilog HDL: BidirecTIonal Pin

This example implements a clocked bidirecTIonal pin in Verilog HDL.
The value of OE determines whether bidir is an input, feeding in inp, or a tri-state, driving out the value b.

module bidirec (oe, clk, inp, outp, bidir);

// Port DeclaraTIon

input   oe;
input   clk;
input   [7:0] inp;
output  [7:0] outp;
inout   [7:0] bidir;

reg     [7:0] a;
reg     [7:0] b;

assign bidir = oe ? a : 8'bZ ;
assign outp  = b;

// Always Construct

always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end

endmodule