library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
entity shicount is
port(clk,reset,enable: in std_logic
a,b,c,d,e,f,g: out std_logic
tp : out std_logic_vector(0 to 3)
xian: out std_logic_vector(0 to 6)
count :out std_logic)
end shicount
architecture xu of shicount is
signal temp :std_logic_vector(0 to 3)
signal xianshi:std_logic_vector(0 to 6)
begin
process(clk,reset,enable)
begin
if (reset='1')then temp<="0000"
elsif (enable='1') then
if (clk' event and clk='1')
then if (temp<="1000") then temp<=temp+1
else temp<="0000"
end if
end if
end if
end process
process(temp)
begin
case temp is
when "0000"=> xianshi<="0000001"count<='0'
when "0001"=> xianshi<="0110000"count<='0'
when "0010"=> xianshi<="1101101"count<='0'
when "0011"=> xianshi<="1111001"count<='0'
when "0100"=> xianshi<="0110011"count<='0'
when "0101"=> xianshi<="1011011"count<='0'
when "0110"=> xianshi<="0011111"count<='0'
when "0111"=> xianshi<="1110000"count<='0'
when "1000"=> xianshi<="1111111"count<='0'
when "1001"=> xianshi<="1110011"count<='1'
when others=> xianshi<="0000000"count<='0'
end case
end process
a<=xianshi(6) b<=xianshi(5) c<=xianshi(4) d<=xianshi(3)
e<=xianshi(2)f<=xianshi(1) g<=xianshi(0) tp<=temp
xian<=xianshi
end xu
library ieeeuse ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
use ieee.std_logic_arith.all
entity jishuqi is
port(cp,en,r,d:in std_logic--d=1 => 加法 d=0 => 减法 en使能端，r复位端
m:in std_logic_vector(1 downto 0)--m 选择进制：00为2进制、01为8进制、10为10进制、11为16进制
t:out std_logic_vector(3 downto 0))
end jishuqi
architecture behave of jishuqi is
signal q:std_logic_vector(3 downto 0)
begin
process(cp,en,r,d,m,q)
begin
if en='0' then
q<="0000"
else
if r='1' then
q<="0000"
else
if cp'event and cp='1' then
if d='1' then
if m="00" then
if q<"0001" then
q<=q+1
else
q<=(others=>'0')
end if
elsif m="01" then
if q<"0111" then
q<=q+1
else
q<=(others=>'0')
end if
elsif m="10" then
if q<"1001" then
q<=q+1
else
q<=(others=>'0')
end if
elsif m="11" then
if q<"1111" then
q<=q+1
else
q<=(others=>'0')
end if
end if
else
if m="00" then
if q>"0000" then
q<=q-1
else
q<="0001"
end if
elsif m="01" then
if q>"0000" then
q<=q-1
else
q<="0111"
end if
elsif m="10" then
if q>"0000" then
q<=q-1
else
q<="1001"
end if
elsif m="11" then
if q>"0000" then
q<=q-1
else
q<="1111"
end if
end if
end if
end if
end if
end if
end process
t<=q
end behave
你如果只要八进制的自己改一下吧！
10110101序列信号发生器.vhdlibrary IEEE
use IEEE.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity count8 is
port (
r: in std_logic
clk: in STD_LOGIC
cout: out std_logic
)
end count8
architecture count8_arch of count8 is
signal dd: std_logic_vector ( 2 downto 0 )
begin
count: process ( r,clk )
begin
if ( r='1' ) then dd<="000"
elsif( clk'event and clk = '1') then
dd <= dd + '1'
end if
end process count
with dd select
cout<='1'when"000",
'0'when"001",
'1'when"010",
'1'when"011",
'0'when"100",
'1'when"101",
'0'when"110",
'1'when"111",
'0'when others
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