vivado提示程序内存错误

内存不足。

vivado软件差凳运行是需要一定量内存的，如果机器内存不够，那就会频繁出现内存溢出报错的情况。

Vivado设计套件，是FPGA厂商赛灵思公司2012年发布的集成设计环境。包括高度集成的设计环境和新一代从系统到IC级的工具，这些均建立在共启汪享的可扩展数据模型和通用调试悄庆仔环境基础上。这也是一个基于AMBAAXI4互联规范、IP-XACTIP封装元数据、工具命令语言(TCL)、Synopsys系统约束(SDC)以及其它有助于根据客户需求量身定制设计流程并符合业界标准的开放式环境。赛灵思构建的Vivado工具把各类可编程技术结合在一起，能够扩展多达1亿个等效ASIC门的设计。

[DRC NSTD-1] Unspecified I/O Standard: 4 out of 134 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO_LED_0[3:0].

[DRC UCIO-1] Unconstrained Logical Port: 4 out of 134 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO_LED_0[3:0].

pin planning error原因是   GPIO_LED_0[3:0]  和xdc文件上的名称不一致  xdc是GPIO_LED[3:0] 。注意观察bd文件中的引脚名称和xdc文件是否一样，或者打开implementation----->layout----->io管脚来观看是否引脚对的。或参考 https://www.eefocus.com/otod3r/blog/14-04/302799_38ddf.html 试试

2.

[BD 41-1356] Address block </math_ip_0/S_AXI/reg0>is not mapped into </processing_system7_0/Data>.。。。。。。。。。。。。。。

错误原因：地址分配有问题，点击其中一个小按钮自动分配下地址就行了

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