求用vhdl语言做个全加器的程序

library ieee

use ieee.std_logic_1164.all

entity f_adder is

port(ain,bin,cin :in std_logic

cout,sum :out std_logic)

end entity f_adder

architecture f1 of f_adder is

component h_adder

port(a,b:in std_logic

co,so:out sud_logic)

end component

component or2a

port(a,b:in std_logic

c:out sud_logic)

end component

signal d,e,f:in std_logic

begin

u1:h_adder port(ain,bin,d,e)

u2:h_adder port(e,cin,f,sum)

u3:or2a port(d,f,cout)

end architecture f1

//一位二进制全加器

library ieee

use ieee.std_logic_1164.all

entity f_adder_4 is

port(a[3,b[3],c[3]] :in std_logic_vector(3 downto 0)

q[3],cout [3]:out std_logic_vector(3 downto 0))

end entity f_adder_4

architecture f2 of f_adder_4 is

component f_adder

port(ain,bin,cin :in std_logic

cout,sum :out std_logic)

end component

sigal a,b,c:std_logic

begin

f1:f_adder port map(a[0],b[0], ,q[0],a)

f2:f_adder port map(a[1],b[1],a,q[1],b)

f3:f_adder port map(a[2],b[2],b,q[2],c)

f4:f_adder port map(a[3],b[3],c,q[3],cout_4)

end architeture f2//四位全加器

1、设计原理

电路结构图或原理图

电路功能描述

定义了8位二进制全加器顶层设计元件端口信号，输入端口：AIN, BIN,是八个二进制数，数据类型被定义为STD_LOGIC_VECTOR。 CIN是输入的进位，数据类型IN STD_LOGIC；输出端口：SUM为和，数据类型IN STD_LOGIC COUT为输出的进位。 定义了7个信号C1, C2, C3,C4,C5,C6,C7作为器件内部的连接线，采用映射语句port map()将8个一位二进制全加器连接起来构成一个完整的全加器。低位全加器进位输出端连到高一位全加器的进位输入端，任何一位的加法运算必须等到低位加法完成时才能进行，这种进位方式称为串行进位

2、实验程序

程序1：半加器描述

功 能：程序功能简介

VHDL源程序代码

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY H_ADDER IS

PORT (A, B : IN STD_LOGIC

CO, SO : OUT STD_LOGIC )

END ENTITY H_ADDER

ARCHITECTURE FH1 OF H_ADDER IS

BEGIN

SO <= NOT (A XOR (NOT B))

CO <= A AND B

END ARCHITECTURE FH1

程序2：一位二进制全加器设计顶层描述

功能：程序功能简介

VHDL源程序代码

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY F_ADDER IS

PORT (AIN, BIN, CIN : IN STD_LOGIC

COUT, SUM : OUT STD_LOGIC )

END ENTITY F_ADDER

ARCHITECTURE FD1 OF F_ADDER IS

COMPONENT H_ADDER IS

PORT (A, B : IN STD_LOGIC

CO, SO : OUT STD_LOGIC )

END COMPONENT

SIGNAL D, E, F : STD_LOGIC

BEGIN

U1 : H_ADDER PORT MAP(A =>AIN, B =>BIN, CO =>D, SO =>E)

U2 : H_ADDER PORT MAP(A =>E, B =>CIN, CO =>F, SO =>SUM)

COUT <= D OR F

END ARCHITECTURE FD1

程序3：8位并行二进制全加器顶层文件

功能：程序功能简介

VHDL源程序代码

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY F_ADDER8 IS

PORT ( AIN, BIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0)

CIN : IN STD_LOGIC

SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

COUT : OUT STD_LOGIC )

END F_ADDER8

ARCHITECTURE ONE OF F_ADDER8 IS

COMPONENT F_ADDER IS

PORT (AIN, BIN, CIN : IN STD_LOGIC

COUT, SUM : OUT STD_LOGIC )

END COMPONENT

SIGNAL C1, C2, C3,C4,C5,C6,C7: STD_LOGIC

BEGIN

U1 : F_ADDER PORT MAP(AIN =>AIN(0), BIN =>BIN(0), CIN =>CIN, SUM =>SUM(0), COUT =>C1)

U2 : F_ADDER PORT MAP(AIN =>AIN(1), BIN =>BIN(1), CIN =>C1, SUM =>SUM(1), COUT =>C2)

U3 : F_ADDER PORT MAP(AIN =>AIN(2), BIN =>BIN(2), CIN =>C2, SUM =>SUM(2), COUT =>C3)

U4 : F_ADDER PORT MAP(AIN =>AIN(3), BIN =>BIN(3), CIN =>C3, SUM =>SUM(3), COUT =>C4)

U5 : F_ADDER PORT MAP(AIN =>AIN(4), BIN =>BIN(4), CIN =>C4, SUM =>SUM(4), COUT =>C5)

U6 : F_ADDER PORT MAP(AIN =>AIN(5), BIN =>BIN(5), CIN =>C5, SUM =>SUM(5), COUT =>C6)

U7 : F_ADDER PORT MAP(AIN =>AIN(6), BIN =>BIN(6), CIN =>C6, SUM =>SUM(6), COUT =>C7)

U8 : F_ADDER PORT MAP(AIN =>AIN(7), BIN =>BIN(7), CIN =>C7, SUM =>SUM(7), COUT =>COUT)

END ONE

好吧，按照你的来

#include<stdio.h>

//AND

int and(int x,int y)

{

if (x*y==1){

return 1

}

else{

return 0

}

}

// OR

int or(int x,int y)

{

if(x+y>=1){

return 1

}

else{

return 0

}

}

//NOT

int not(int x)

{

if(x==1){

return 0

}

else{

return 1

}

}

//XOR

int xor(int a,int b)

{

int xor_value

xor_value=or(and(not(a),b),and(a,not(b)))

return xor_value

}

// half adder sum

int sum_ha(int a, int b)

{

return xor(a,b)

}

//half adder carry

int carry_ha(int a,int b)

{

return and(a,b)

}

// full adder sum

int sum_fu(int a, int b, int x)

{

return ( xor( xor(a,b),x) )

}

// full adder carry

int carry_fu(int a, int b,int x)

{

return ( or( carry_ha(a, b), and( sum_ha(a, b), x ) ) )

}

int main(void)

{

int x,y,z

printf("Enter two logical values and x:")

scanf("%1d%1d%ld",&x,&y,&z)

printf( "Sum=%1d\n", sum_fu(x,y,z) )

printf("carry=%1d\n",carry_fu(x,y,z))

return 0

}

这个是查表法

#include <stdio.h>

typedef struct{

unsigned A:1

unsigned B:1

unsigned X:1

unsigned C:1

unsigned S:1

}LOG

LOG logical_table[]={

/* 全加器 真值表 */

/* A B XC S */

{0, 0, 0, 0, 0 },

{0, 0, 1, 0, 1 },

{0, 1, 0, 0, 1 },

{0, 1, 1, 1, 0 },

{1, 0, 0, 0, 1 },

{1, 0, 1, 1, 0 },

{1, 1, 0, 1, 0 },

{1, 1, 1, 1, 1 },

}

int main(void)

{

unsigned a,b,x,c, s

int i

printf("Enter a,b,and x: ")

scanf("%u%u%u",&a,&b,&x)

for(i=0i<sizeof(logical_table)/sizeof(logical_table[0])i++)

{

if( a == logical_table[i].A &&\

b == logical_table[i].B &&\

x == logical_table[i].X )

{

c = logical_table[i].C

s = logical_table[i].S

}

}

printf("Carry:%uSum:%u\n",c, s)

return 0

}

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