怎么用VHDL设计一位全加器啊？急急急！求程序！

一位全加前笑穗慧卜器源代码如升薯下：

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

use ieee.std_logic_arith.all

entity bit1adder is

port(

a,b,ci:in std_logic

s,co:out std_logic

)

end bit1adder

architecture func of bit1adder is

signal:x,y:std_logic

begin

x<=a xor b

y<=x and ci

s<=x xor ci

co<=y or (a and b)

end func

一位全加器裤羡源代码如下：

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

use ieee.std_logic_arith.all

entity bit1adder is

port(

a,b,ci:in std_logic

s,co:out std_logic

)

end bit1adder

architecture func of bit1adder is --此功能可由真值表推出，或者亦可直接列出真值表代替此程序

signal:x,y:std_logic

begin

x<=a xor b

y<=x and ci

s<=x xor ci

co<=y or (a and b)

end func

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二位全加器源代码如下：

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

use ieee.std_logic_arith.all--此包含有类型败纯肆转换函数

entity bit2adder is

port(

a,b:in std_logic_vector(1 downto 0)

ci:in std_logic

co:out std_logic

s:out std_logic_vector(1 downto 0)

)

end bit2adder

architecture func of bit2adder is

begin

process(a,b,ci) --更多位的也可按照此思路来写

variable temp:std_logic_vector(2 downto 0)

variable x,y,sum:ingeter

begin

x:=conv_integer(a)

y:=conv_integer(b)

sum:=(x+y)+conv_integer(ci)

temp:=conv_std_logic_vector(sum,3)

s<=temp(1 downto 0)

co<=temp(2)

end process

end func

VHDL语言如梁衡设计四位全加器：

library IEEE

use IEEE.Std_logic_1164.ALL

entity pro1 is

port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic

Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic)

end pro1

architecture pro1_arch of pro1 is

begin

Y10<='0' when(B0='0') and ((A0='0') and (G0BAR='0')) else '1'

Y11<='0' when(B0='0') and ((A0='1') and (G0BAR='0')) else '1'

Y12<渣做='0' when(B0='1') and ((A0='0') and (G0BAR='0')) else '1'

Y13<='0' when(B0='1') and ((A0='1') and (G0BAR='0')) else '1'

Y20<='0' when(B1='0') and ((A1='0') and (G1BAR='0')) else '1'

Y21<='0' when(B1='0') and ((A1='1') and (G1BAR='0')) else '1'

Y22<='0' when(B1='1') and ((A1='0') and (G1BAR='0')) else '1'

Y23<='0' when(B1='1') and ((A1='1') and (G1BAR='0')) else '1'

end pro1_arch

能实现四位二进制数全加的数字电渣租路模块，称之为四位全加器。

http://baike.baidu.com/link?url=GaCnz6D-_GQfu1rs_YfE_cZKiwRMcRtEpeLDS2Nn-0UlA39xIq_E2Vw8ttNptjB-kaKIblYblcLCXucw3cbaIK

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